Study Plans — DV Interview Handbook

📊 Progress

⚡ 2-Week Intensive Plan

Best for: You have an interview in ~2 weeks and need to cover the essentials fast. Assumes 4-6 hours/day of focused study.

📅 Week 1 — Foundations & Core

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Day 1 — OOP + SV Basics

Review OOP: inheritance, polymorphism, encapsulation, virtual methods

SV data types: logic, reg, wire, bit, enum, struct, typedef

SV arrays: dynamic, associative, queues, packed vs unpacked

Day 2 — SV Processes & Interfaces

fork-join, fork-join_any, fork-join_none, wait fork, disable fork

Interfaces, modports, clocking blocks, virtual interfaces

IPC: mailboxes, semaphores, events — practice 3 code examples

Day 3 — Constraints & Randomization

rand vs randc, inline constraints, solve-before, distribution

Constraint blocks, soft constraints, unique, pre/post_randomize

Practice: solve 20 constraint coding questions

Day 4 — Assertions & Coverage

Immediate vs concurrent assertions, $rose, $fell, $stable

Sequences, properties, SVA operators (##, |=>, |->)

Covergroups, coverpoints, cross coverage, bins

Day 5 — UVM Part 1

UVM testbench architecture: test → env → agent → driver/monitor

UVM phases: build, connect, run, report

Sequences, sequencer, sequence items, body() task

Day 6 — UVM Part 2

TLM ports, FIFOs, analysis ports, scoreboards

RAL model: registers, register blocks, frontdoor vs backdoor

Config DB, factory overrides, virtual sequences

Day 7 — Review & Mock Test

Review all SV + UVM notes from the week

Take Mock Test: SV + UVM + Constraints categories

Revise weak areas identified from mock test

📅 Week 2 — Architecture, Protocols & Practice

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Day 8 — Computer Architecture Part 1

5-stage pipeline, hazards (data/control/structural), forwarding

Cache: direct-mapped, set-associative, replacement policies

Memory hierarchy: SRAM, DRAM, virtual memory, TLB

Day 9 — Computer Architecture Part 2

Branch prediction, out-of-order execution, Tomasulo's algorithm

RISC vs CISC, instruction formats, addressing modes

Cache coherence: MESI protocol, snooping, directory-based

Day 10 — STA & CDC

Setup & hold time analysis, critical path, slack

Clock domain crossing, metastability, synchronizers

Gray code, handshake synchronizers, FIFO-based CDC

Day 11 — Protocols

SPI: master/slave, CPOL/CPHA, timing diagrams

I2C: addressing, ACK/NACK, start/stop conditions

AXI: channels, handshake, burst types, AXI-Lite vs full AXI

Day 12 — FSM + Python

Mealy vs Moore, state encoding, FSM verification approaches

Python: scripting basics, log parsing, regex, file I/O

Practice: 5 common FSM interview problems

Day 13 — Full Mock Interview

Take full Mock Test (all topics, all companies)

Review Real Interview Experiences page — study company patterns

Prepare "Tell me about yourself" and project walkthroughs

Day 14 — Final Review

Quick review of all flashcard "Don't Know" items

Review resume — make sure you can explain every bullet point

Rest, stay calm, and visualize success 🎯

📚 1-Month Comprehensive Plan

Best for: You have ~4 weeks before interviews begin. Covers everything in depth with practice. Assumes 3-4 hours/day of study.

📅 Week 1 — SystemVerilog Deep Dive

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Days 1-2 — OOP & SV Fundamentals

OOP: classes, inheritance, polymorphism, virtual methods, abstract classes

SV data types: logic, reg, wire, bit, enum, struct, union, typedef

Arrays in depth: dynamic, associative, queues, array methods

Practice: write 5 small programs on EDA Playground

Days 3-4 — Processes, Interfaces & IPC

Processes: fork-join variants, wait fork, disable fork

Interfaces, modports, clocking blocks, virtual interfaces

IPC: mailboxes, semaphores, events — code examples

Practice: producer-consumer using mailbox on EDA Playground

Days 5-6 — Constraints & Randomization

rand, randc, constraint blocks, inline constraints

solve-before, soft constraints, distribution, unique

pre_randomize(), post_randomize(), constraint mode

Practice: solve 30+ constraint coding questions from PDF

Day 7 — Assertions & Coverage

Immediate vs concurrent assertions, assertion directives

SVA sequences, properties, $rose, $fell, $stable, ##, |=>, |->

Covergroups, coverpoints, cross coverage, bins, transitions

Practice: 15 SVA assertion problems with solutions

Take SV Mock Test — identify weak areas

Review and revisit weak topics from the week

📅 Week 2 — UVM Framework Mastery

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Days 8-9 — UVM Architecture

UVM testbench hierarchy: test, env, agent, driver, monitor

UVM phases: build_phase, connect_phase, run_phase, report_phase

UVM config_db: set vs get, wildcard paths, precedence

UVM factory: type overrides, instance overrides, use cases

Days 10-11 — Sequences & TLM

Sequence items, sequences, body() task, starting sequences

Virtual sequences, sequence library, p_sequencer

TLM ports: blocking/nonblocking, analysis ports, FIFOs

Scoreboards: comparators, predictors, checking strategies

Days 12-13 — RAL & Advanced UVM

RAL model: uvm_reg, uvm_reg_block, register map

Frontdoor vs backdoor access, built-in sequences

UVM objections, drain time, timeouts, reporting macros

Practice: draw UVM testbench diagram from memory

Day 14 — Review

Take UVM Mock Test — review all wrong answers

Review UVM Udemy project — trace flow from test to DUT

Prepare to explain a UVM testbench you've built in interviews

📅 Week 3 — Architecture, STA & Protocols

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Days 15-16 — Computer Architecture

Pipelining: 5-stage, hazards, forwarding, stalling

Cache: types, replacement policies, write-back vs write-through

Memory hierarchy, virtual memory, TLB, page tables

Branch prediction, OoO execution, Tomasulo, reorder buffer

Days 17-18 — Architecture Part 2 + STA

RISC vs CISC, ISA, instruction formats, addressing modes

Cache coherence: MESI, snooping, directory protocols

STA: setup time, hold time, critical path, slack calculation

Practice: solve 10 STA timing calculation problems

Days 19-20 — CDC & Protocols

CDC: metastability, 2-FF synchronizer, gray code counters

Handshake synchronizers, async FIFO (read/write pointer)

SPI: CPOL/CPHA, timing; UART: baud rate, framing

I2C: start/stop, addressing, ACK/NACK, multi-master

Day 21 — AXI & Review

AXI: 5 channels, handshake (VALID/READY), burst types

AHB: single/burst transfers, HREADY, pipeline

Take CA + STA + Protocols Mock Test

Review weak areas, revisit confusing concepts

Read 2 Real Interview Experiences (study the pattern)

Prepare project walkthrough — practice explaining out loud

📅 Week 4 — Final Prep & Mock Interviews

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Days 22-23 — FSM, Python & Gaps

FSM: Mealy vs Moore, encoding, verification strategies

Practice: 5 FSM design + verification problems

Python: scripting, regex, log parsing, data structures

Revisit any weak topics from previous mock tests

Days 24-25 — Full Mock Interviews

Full Mock Test — all topics, simulate real interview timing

Review all "Don't Know" and "Review" flashcards

Read all Real Interview Experiences — note common patterns

Practice: whiteboard-style problem solving (draw & explain)

Days 26-27 — Resume & Behavioral

Finalize resume — tailor for target company roles

Prepare behavioral answers: tell me about yourself, biggest challenge, teamwork

Practice explaining your projects in 2-minute walkthroughs

Prepare 5 questions to ask the interviewer

Days 28-30 — Final Review & Rest

Quick skim of all topic cheatsheets and notes

One final Mock Test — aim for 80%+ confidence on all topics

Review resume one last time — be able to explain every line

Organize interview logistics (company research, time zones)

Rest well, stay confident — you've put in the work! 🎯

✅ You're ready. Go ace that interview!

Pair Your Plan With These

Use these resources alongside your study plan for maximum impact.

🧠 Mock Test 📚 Topic Guide 🎤 Real Interviews 📄 Resume Guide

📋 Study Plans

⚡ 2-Week Intensive Plan

📅 Week 1 — Foundations & Core

📅 Week 2 — Architecture, Protocols & Practice

📚 1-Month Comprehensive Plan

📅 Week 1 — SystemVerilog Deep Dive

📅 Week 2 — UVM Framework Mastery

📅 Week 3 — Architecture, STA & Protocols

📅 Week 4 — Final Prep & Mock Interviews

Pair Your Plan With These