📚 Topic Guide

Why it matters: SystemVerilog is the backbone of modern verification. Every DV interview will have SV questions.

Key Topics to Cover:

• Data Types — logic, reg, wire, bit, byte, int, shortint, longint, enum, struct, union, typedef
• Arrays — Dynamic arrays, associative arrays, queues, packed vs unpacked
• Processes — fork-join, fork-join_any, fork-join_none, wait fork, disable fork
• Interfaces — Modports, clocking blocks, virtual interfaces
• Randomization — rand, randc, constraint blocks, pre/post_randomize()
• Coverage — Covergroups, coverpoints, cross coverage, bins
• Classes & OOP — Constructors, inheritance, virtual methods, parameterized classes
• Interprocess Communication — Mailboxes, semaphores, events

📎 Resources:

• ChipVerify — SystemVerilog Tutorial
• Verification Guide — SV Tutorial

Why it matters: UVM is the industry-standard verification methodology. Understanding the testbench architecture is crucial.

Key Topics to Cover:

• UVM Testbench Architecture — Environment, agent, driver, monitor, sequencer, scoreboard
• UVM Phases — Build, connect, run, extract, check, report
• Sequences — uvm_sequence, uvm_sequence_item, body(), start()
• TLM Ports — Analysis ports, FIFOs, put/get ports, exports
• Factory — Type overrides, instance overrides, create()
• Configuration DB — uvm_config_db set/get, resource database
• RAL Model — Register abstraction layer, front-door/back-door access
• Virtual Sequences — Multi-agent coordination, virtual sequencer
• Callbacks & Objections — Phase objections, drain time, callbacks

📎 Resources:

• ChipVerify — UVM Tutorial
• Verification Guide — UVM Tutorial
• 🌟 Udemy — UVM for Verification: Projects (Recommended) — Hands-on projects that help you truly understand UVM testbench architecture

Why it matters: Timing and CDC bugs are silicon killers. Interviewers love these topics.

STA — Static Timing Analysis:

• Setup & Hold Time — Definitions, violations, fixing strategies
• Clock Skew & Jitter — Impact on timing, positive vs negative skew
• Slack — Setup slack, hold slack, worst negative slack (WNS)
• Multi-cycle Paths — False paths, multi-cycle path constraints
• Clock Trees — CTS, clock gating, clock dividers

CDC — Clock Domain Crossing:

• Metastability — What causes it, MTBF calculation
• Synchronizers — 2-FF synchronizer, pulse synchronizer
• Gray Code — Why used for CDC, FIFO pointer crossing
• Async FIFO — Design, verification, depth calculation
• Handshake-based CDC — Req-ack mechanism

📎 Resources:

• YouTube — STA Lectures
• YouTube — CDC Lectures
• Cummings CDC Papers (SNUG)

Why it matters: Protocol knowledge shows you can verify real-world interfaces. AXI/AHB are very common in SoC verification.

SPI (Serial Peripheral Interface):

• Master-slave architecture, MOSI/MISO/SCLK/SS signals
• Clock polarity (CPOL) and phase (CPHA) modes
• Full-duplex communication

UART:

• Asynchronous, start/stop bits, baud rate
• Parity bit, frame format, flow control

I2C:

• Two-wire (SDA, SCL), multi-master, addressing
• Start/stop conditions, ACK/NACK, clock stretching

AXI (Advanced eXtensible Interface):

• 5 channels: AW, W, B, AR, R
• Burst types (FIXED, INCR, WRAP), handshake (VALID/READY)
• Outstanding transactions, out-of-order responses

AHB (Advanced High-performance Bus):

• Single master pipeline, HTRANS, HSIZE, HBURST
• HREADY, HRESP, split/retry

Why it matters: Constraint-writing questions are guaranteed in DV interviews. You'll be asked to write constraints on the spot.

Key Topics to Cover:

• Constraint Blocks — Inside vs outside class, constraint_mode()
• Inline Constraints — randomize() with { ... }
• Distributions — :/ and := operators
• Solve Before — Ordering constraint solving
• Unique Constraints — Generating unique values
• Conditional Constraints — if-else, implication (->)
• Array Constraints — size, sum, foreach
• Soft Constraints — Overridable defaults

💡 Practice Problems:

• Write a constraint to generate a unique array of 10 elements between 1 and 100
• Constrain a packet to have a valid CRC
• Generate an address aligned to 4-byte boundary
• Write a constraint where if mode==READ, data should be 0

📎 Resources:

• 📖 100+ Constraint Interview Questions (PDF)

Why it matters: SVA is critical for formal verification and catching protocol bugs. Expect whiteboard assertion questions.

Key Topics to Cover:

• Immediate Assertions — assert, assume, cover
• Concurrent Assertions — property, sequence, @(posedge clk)
• Temporal Operators — ##N, |-> (overlapping), |=> (non-overlapping)
• Repetition — [*N], [*M:N], [->N] (goto), [=N] (non-consecutive)
• System Functions — $rose, $fell, $stable, $past, $countones
• Disable Iff — Reset handling in assertions

💡 Practice Problems:

• Write an assertion: if req goes high, ack must come within 1-5 cycles
• Assert that data remains stable while valid is high
• Write a cover property for back-to-back transactions

📎 Resources:

• 📖 25+ SVA Assertion Practice Problems with Solutions (PDF)

Why it matters: SV and UVM are built on OOP. Understanding OOP is foundational.

Key Topics to Cover:

• Encapsulation — Public, protected, local access modifiers
• Inheritance — extends, super, constructor chaining
• Polymorphism — Virtual methods, dynamic dispatch, $cast
• Abstract Classes — Pure virtual methods
• Parameterized Classes — Type parameters, #(type T = int)
• Shallow vs Deep Copy — Copy semantics, custom copy()
• Handle vs Object — Reference semantics in SV

Why it matters: Python scripting is increasingly important for log parsing, automation, and regression management.

Key Topics to Cover:

• Data Structures — Lists, dictionaries, sets, tuples
• String Manipulation — Regex, split, join, formatting
• File I/O — Reading/writing files, CSV, JSON parsing
• List Comprehensions — Filtering, mapping in one line
• Functions — *args, **kwargs, lambda, decorators
• OOP in Python — Classes, inheritance, dunder methods
• Scripting — os, subprocess, argparse, sys modules
• Regular Expressions — re module, pattern matching for log parsing

📎 Resources:

• W3Schools — Python Tutorial

Why it matters: FSMs are the building block of digital design. You'll be asked to design and verify FSMs.

Key Topics to Cover:

• Mealy vs Moore — Output depends on state+input vs state only
• State Encoding — Binary, one-hot, gray code, pros & cons
• FSM Coding Styles — 1-block, 2-block, 3-block
• Common FSMs — Traffic light controller, vending machine, sequence detector
• FSM Verification — Coverage of states & transitions, corner cases
• Deadlock and Livelock — Detection and prevention

Why it matters: "Cracking Digital VLSI Verification Interview" by Ramdas M & Robin Garg is the gold-standard reference for DV interviews — 500+ questions with detailed solutions covering Digital Logic, Computer Architecture, Programming, SystemVerilog, UVM, Assertions, Coverage, and Behavioral questions.

Suggested Focus Areas:

• Verification planning and coverage-driven methodology
• Constrained random verification approach
• Testbench architecture patterns
• Advanced SV/UVM concepts
• Debug techniques and strategies
• Non-technical and behavioral interview questions

📎 Resources:

• 📖 Read / Download — Cracking Digital VLSI Verification Interview (PDF)