Why it matters

Computer architecture questions test your fundamental understanding of how processors work — a must for any DV role at chip companies. Expect questions on pipelines, caches, and memory ordering in nearly every loop.

Core concepts

• Pipelining — 5-stage pipeline, hazards (data, control, structural), forwarding, stalling
• Cache memory — Direct-mapped, set-associative, fully-associative, replacement policies, write-back vs write-through
• Memory hierarchy — SRAM, DRAM, virtual memory, TLB, page tables
• Branch prediction — Static vs dynamic, BHT, BTB, 2-bit predictors
• Out-of-order execution — Tomasulo's algorithm, reorder buffer, reservation stations
• Instruction set architecture — RISC vs CISC, instruction formats, addressing modes
• Multi-core & coherence — MESI protocol, snooping, directory-based coherence

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Why it matters

SystemVerilog is the language of verification. If you can't reason about fork-join, clocking blocks, and constraint solving on the spot, you will struggle.

Core concepts

• Data types — logic, reg, wire, bit, byte, int, shortint, longint, enum, struct, union, typedef
• Arrays — Dynamic arrays, associative arrays, queues, packed vs unpacked
• Processes — fork-join, fork-join_any, fork-join_none, wait fork, disable fork
• Interfaces — Modports, clocking blocks, virtual interfaces
• Randomization — rand, randc, constraint blocks, pre/post_randomize()
• Coverage — Covergroups, coverpoints, cross coverage, bins
• Classes & OOP — Constructors, inheritance, virtual methods, parameterized classes
• Interprocess communication — Mailboxes, semaphores, events

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Why it matters

UVM is the industry-standard verification methodology. Understanding the testbench architecture is crucial — interviewers will ask you to draw it from scratch.

Core concepts

• Testbench architecture — Environment, agent, driver, monitor, sequencer, scoreboard
• UVM phases — Build, connect, run, extract, check, report
• Sequences — uvm_sequence, uvm_sequence_item, body(), start()
• TLM ports — Analysis ports, FIFOs, put/get ports, exports
• Factory — Type overrides, instance overrides, create()
• Configuration DB — uvm_config_db set/get, resource database
• RAL model — Register abstraction layer, front-door/back-door access
• Virtual sequences — Multi-agent coordination, virtual sequencer
• Callbacks & objections — Phase objections, drain time, callbacks

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Why it matters

Timing and CDC bugs rarely show up in simulation but hit you in silicon. Interviewers use these topics to separate candidates who understand digital fundamentals from those who don't.

Static Timing Analysis (STA)

• Setup & hold time — Definitions, violations, fixing strategies
• Clock skew & jitter — Impact on timing, positive vs negative skew
• Slack — Setup slack, hold slack, worst negative slack (WNS)
• Multi-cycle paths — False paths, multi-cycle path constraints
• Clock trees — CTS, clock gating, clock dividers

Clock Domain Crossing (CDC)

• Metastability — What causes it, MTBF calculation
• Synchronizers — 2-FF synchronizer, pulse synchronizer
• Gray code — Why used for CDC, FIFO pointer crossing
• Async FIFO — Design, verification, depth calculation
• Handshake CDC — Req-ack mechanism

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Why it matters

Protocol knowledge shows you can verify real-world interfaces. AXI and AHB are very common in SoC verification — you'll almost certainly be asked to explain a VALID/READY handshake.

SPI — Serial Peripheral Interface

• Master-slave architecture, MOSI/MISO/SCLK/SS signals
• Clock polarity (CPOL) and phase (CPHA) modes
• Full-duplex communication

UART

• Asynchronous, start/stop bits, baud rate
• Parity bit, frame format, flow control

I²C

• Two-wire (SDA, SCL), multi-master, addressing
• Start/stop conditions, ACK/NACK, clock stretching

AXI — Advanced eXtensible Interface

• 5 channels: AW, W, B, AR, R
• Burst types (FIXED, INCR, WRAP), handshake (VALID/READY)
• Outstanding transactions, out-of-order responses

AHB — Advanced High-performance Bus

• Single-master pipeline, HTRANS, HSIZE, HBURST
• HREADY, HRESP, split/retry

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Why it matters

Constraint-writing shows up on every interview — from simple ranges to tricky solve before ordering. Practicing these until they are second nature pays off.

Core concepts

• Constraint blocks — Inside vs outside class, constraint_mode()
• Inline constraints — randomize() with { ... }
• Distributions — :/ and := operators
• Solve before — Ordering constraint solving
• Unique constraints — Generating unique values
• Conditional constraints — if-else, implication (->)
• Array constraints — size, sum, foreach
• Soft constraints — Overridable defaults

Practice problems

• Write a constraint to generate a unique array of 10 elements between 1 and 100.
• Constrain a packet to have a valid CRC.
• Generate an address aligned to a 4-byte boundary.
• Write a constraint where if mode == READ, data should be 0.

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Why it matters

A well-written assertion catches a bug that a scoreboard would miss. Interviewers use SVA to test whether you think temporally.

Core concepts

• Immediate assertions — assert, assume, cover
• Concurrent assertions — property, sequence, @(posedge clk)
• Temporal operators — ##N, |-> (overlapping), |=> (non-overlapping)
• Repetition — [*N], [*M:N], [->N] (goto), [=N] (non-consecutive)
• System functions — $rose, $fell, $stable, $past, $countones
• Disable iff — Reset handling in assertions

Practice problems

• Write an assertion: if req goes high, ack must come within 1–5 cycles.
• Assert that data remains stable while valid is high.
• Write a cover property for back-to-back transactions.

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Why it matters

SV and UVM are built on OOP. Understanding OOP is foundational — without it, UVM will feel like magic instead of engineering.

Core concepts

• Encapsulation — public, protected, local access modifiers
• Inheritance — extends, super, constructor chaining
• Polymorphism — Virtual methods, dynamic dispatch, $cast
• Abstract classes — Pure virtual methods
• Parameterized classes — Type parameters, #(type T = int)
• Shallow vs deep copy — Copy semantics, custom copy()
• Handle vs object — Reference semantics in SV

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Why it matters

Python is the scripting language of modern verification flows — log parsing, regression management, result crunching, infrastructure glue.

Core concepts

• Data structures — Lists, dictionaries, sets, tuples
• String manipulation — Regex, split, join, formatting
• File I/O — Reading/writing files, CSV, JSON parsing
• List comprehensions — Filtering, mapping in one line
• Functions — *args, **kwargs, lambda, decorators
• OOP in Python — Classes, inheritance, dunder methods
• Scripting — os, subprocess, argparse, sys modules
• Regular expressions — re module, pattern matching for log parsing

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Why it matters

FSMs are everywhere in digital design. Expect to design a sequence detector or a traffic-light controller live.

Core concepts

• Mealy vs Moore — Output depends on state+input vs state only
• State encoding — Binary, one-hot, gray code — pros & cons
• FSM coding styles — 1-block, 2-block, 3-block
• Common FSMs — Traffic light controller, vending machine, sequence detector
• FSM verification — Coverage of states & transitions, corner cases
• Deadlock and livelock — Detection and prevention

Why it matters

This book covers Digital Logic, Computer Architecture, Programming, SystemVerilog, UVM, Assertions, Coverage, and Behavioral questions — 500+ of them with detailed solutions.

Suggested focus areas

• Verification planning and coverage-driven methodology
• Constrained random verification approach
• Testbench architecture patterns
• Advanced SV/UVM concepts
• Debug techniques and strategies
• Non-technical and behavioral interview questions

Where to get it