🎤 Real Interview Experiences

Actual questions asked in DV engineer interviews at top companies — organized by round

💡 How to use this page: Go through each interview experience end-to-end like a mock interview. Time yourself — 45-60 minutes per round. If you can answer 80%+ of the questions in each round, you're interview-ready.

🧠 CPU / Core DV — Full Interview Loop

CPU DV Engineer — Panel Interview

2 Screening Rounds + 5 Panel Rounds (C++, Architecture, SystemVerilog)

📞 Screening Round 1 — Architecture + Coding (1 hr)

Arch + Verilog
  • RISC-V Pipeline — Explain the 5-stage pipeline for RISC-V
  • Memory Disambiguation — What is it? How does the processor handle it?
  • LSQ Entry — Does the Load Store Queue entry have a virtual address or physical address? Which is better and why?
  • Virtual Memory — Why do we need virtual memory?
  • Cache Verification — How would you verify a direct-mapped cache?
  • Cache Indexing — Given a cache configuration, how many tag bits? Index bits?
  • Cache Configuration — Which cache configuration is better? (Direct-mapped vs set-associative trade-offs)
  • C++ Coding — Given a number, count the number of ones in its binary representation
  • Verilog Coding — Write a Decoder and Encoder in Verilog. How would that change if written in SystemVerilog?

📞 Screening Round 2 — Verification + SV (1 hr)

SV + Coverage
  • Verification Metrics — What metrics do you use to measure verification completeness?
  • Coverage — Why coverage? What are the different types of coverage?
  • Project Discussion — Deep dive into your projects and contributions
  • Constraint Writing — Write constraints for an array which contains a specific number and size of array < 10
  • Constraint Writing — Randomize an array with unique elements and size < 10 (without using randc)
  • Fork/Join Puzzle — for(int i=0; i<3; i++)
      fork $display("%d", i);
      join
    $display("End");     What is printed? Think about fork-join semantics and variable scope.

🔴 Panel Round 1 — Entirely C++ (1 hr)

C++ Deep Dive
  • Static Variables — What are static variables in C++?
  • Stack vs Heap — Explain the difference
  • Object Memory — Where are objects allocated memory?
  • Class Definition — Where is a class definition allocated memory?
  • Function Call — What happens to memory when you call a function?
  • Polymorphism — Polymorphism in C++ vs SystemVerilog — differences?
  • malloc vs new — Difference between malloc and new operator
  • Stack Allocation — How would you force memory to be allocated on stack? Hint: _alloca function for variable-length stack allocation
  • Global Variables — Where are global variables allocated in memory?
  • References vs Pointers — Differences? Why use references and where? References: alias for existing variable, can't be null, pass by value. Pointers: store address, can be null, pass by reference.
  • memcpy of Pointers — Code analysis: what does this memcpy do?
  • Byte Swap Coding — Write code: input 0x12345678 → output 0x78563412

🔴 Panel Round 2 — Architecture (1 hr)

Comp Arch
  • Project Discussion — Deep dive into projects (spent significant time here)
  • Branch Prediction — Explain branch prediction techniques
  • RISC-V Pipeline — Walk through the pipeline stages
  • RAW Hazards — How would you handle Read-After-Write hazards?

🔴 Panel Round 3 — ISA & Virtual Memory (1 hr)

ISA + VM
  • Variable Length ISA — What is a variable-length ISA?
  • Why Variable Length? — Why would you want that ISA?
  • Architecture Changes — What changes in architecture would be needed to support it?
  • Decoding Logic — How would decoding logic change?
  • Virtual Memory — Why virtual memory?
  • Address Translation — How would the translation happen?
  • Page Table Entry — What does a page table entry consist of?
  • Page Size Impact — How does page size affect the system?

🔴 Panel Round 4 — Cache + Assembly + Coding (1 hr)

Heavy Round
  • Virtual Memory — Deep dive into virtual memory concepts
  • Page Fault — What happens on a page fault?
  • Cache Indexing — Multiple cache indexing questions
  • Assembly Analysis — Analyze given assembly code
  • Cache Miss Rate — How to improve cache miss rate?
  • Hit Time — How to improve cache hit time?
  • Cache Verification — Write stimulus to verify a write-back cache
  • Cache Invalidation — There's an instruction that invalidates a cache block (no writeback). How would you verify the invalidation? Hint: Use paging — page the data out and back in to check if invalidated data is truly gone
  • Page Table Entry — What does a page table entry contain?
  • Page Swap — How does page swap happen?
  • C++ Coding — Given array of size n where each element < n, find the repeating element Brute force: hashmap. Optimal: Floyd's cycle detection algorithm (LeetCode pattern)
  • Assembly Code Analysis — Analyze a bubble sort implemented in x86 assembly with register guide provided:
    start_code: xor eax, eax // eax = 0 mov ebx, 5 // ebx = 5 start_loop: mov esi, eax // esi = eax add esi, 1 // esi = eax + 1 mov ecx, [data + eax*4] cmp ecx, [data + esi*4] jle continue mov edx, [data + esi*4] mov [data + esi*4], ecx mov [data + eax*4], edx continue: inc eax cmp eax, ebx jl start_loop cmp ebx, 0 je done dec ebx xor eax, eax jmp start_loop done: hlt data (@ 0x9000): 05 04 03 02 01 00
    It's a bubble sort! Then asked: modify to cause cache misses in direct-mapped (64K, 64B/line) and 8-way associative caches

🔴 Panel Round 5 — SV + Architecture Mix (1 hr)

SV + Arch
  • Out-of-Order Pipeline — Explain how an instruction executes in an OoO pipeline
  • Register Renaming — How does register renaming work?
  • RISC vs CISC — Differences? Why RISC?
  • Cache Miss — What happens on a cache miss for a load instruction?
  • Interrupts — What are interrupts? How do you handle them? Events requiring temporarily stopping program execution to service the event
  • Exceptions — What are exceptions? What happens to the pipeline? Synchronous: invalid opcode, arithmetic overflow, TLB miss, page fault
  • Redirects — What are redirects? (Uncommon question!) Even the professor didn't know this one — don't worry if you can't answer everything
  • Verilog Coding — Write code to add two numbers in Verilog
  • Verilog → SV — How would you change this code for SystemVerilog?
  • Tasks vs Functions — When to use each?
  • Static vs Automatic — What are static variables vs automatic variables in SV?
  • Function Variables — Where are variables stored when you call an SV function?
  • Fork/Join — Various fork/join questions
🔧 SoC DV — Full-Time Interview Loop

SoC DV Engineer — 6 Rounds (45 min each)

Covers Architecture, Digital Logic, SV/UVM, Coding, and Verification Methodology

🔵 Round 1 — Architecture + UVM + Coding

Mixed
  • Virtual Memory — Explain virtual memory concepts
  • Cache — Why do we need caches?
  • UVM Cross-VIP — Include an agent/packet of another VIP in the env of another VIP. How do you extend and use the scoreboard by extending the latter one?
  • Reverse Linked List — Write code to reverse a linked list
  • LCA (Lowest Common Ancestor) — Given 2 nodes in a tree, find the common parent node
  • 2D Array Rotation — Rotate a 2D array by 90 degrees

🔵 Round 2 — Digital Logic + FSM + FIFO

Digital
  • Boolean Reduction — Reduce: A'B + ABC + BC'
  • MUX with X — Write Verilog code for MUX with sel line as X. What happens?
  • Sequence Detector — 1011 sequence detector FSM (both Mealy and Moore)
  • Divide by 5 — How would you implement a divide-by-5 circuit?
  • FIFO Depth Calculation — Producer = 30MHz, Consumer = 50MHz, Items = 120, Idle cycles: read = 3, write = 1
  • Why FIFO? — When and why do you need a FIFO?
  • Signed Numbers — Signed number representation in binary
  • Barrel Shifter — Implement a barrel shifter using MUX

🔵 Round 3 — Timing + Cache + Pipeline

STA + Arch
  • Swap Without Temp — Swap two values in Verilog without a temp variable
  • Power of 2 — Check if a number is a power of 2
  • Setup & Hold — Explain setup time and hold time
  • Hold Violation Fix — How to overcome a hold violation?
  • Stuck-at-0 Fault — 1000 wires to a black box with stuck-at-0 fault — how many test patterns needed?
  • 4-way Set Associative — Given a 4-way set-associative cache, find offset bits, tag bits, set bits
  • Why Cache? — Explain the need for caches
  • Why Pipeline? — Why do we pipeline processors?
  • Hazards — What are hazards and how to overcome them?
  • Pipeline Throughput — 100 instructions, 1 clock per stage — how many clocks for all 100 instructions?

🔵 Round 4 — OOP + SystemVerilog

SV/OOP
  • Polymorphism — Explain polymorphism with examples in SV
  • Automatic Keyword — What does the automatic keyword do in SystemVerilog?

🔵 Round 5 — Cache + Verification

Verification
  • Cache Deep Dive — Various cache-related questions
  • Reference Model — Design a reference model for a round-robin arbiter

🔵 Round 6 — UVM Deep Dive

UVM
  • UVM Testbench — Deep dive into UVM architecture, phases, factory, sequences
  • This was described as the toughest round — make sure you know UVM inside out!
🍎 Apple — GPU DV Screening

Apple GPU DV — Screening Round

Architecture + SystemVerilog OOP + Coding

📞 Screening — Arch + SV + Coding

Apple

Computer Architecture:

  • 5-Stage Pipeline — Walk through all 5 stages
  • Hazards — All types and solutions
  • Reorder Buffer (ROB) — What is it? Why do we need it?

SystemVerilog OOP:

  • Polymorphism — Explain with code example
  • Abstraction — What and why?
  • Inheritance — How does it work in SV?
  • Polymorphism Problem — Code analysis problem on virtual methods
  • Static Variable Access — How to alter a static variable without using a class handle? Answer: Class_name::variable

Coding:

  • Fibonacci — Find the nth value from the Fibonacci series
🍎 Apple — DV Screening

Apple DV — Screening Round

Project Discussion + Cache Coherence + Verilog Coding

📞 Screening — Projects + Architecture + Coding

Apple
  • Current Work — What are you working on? (Project deep dive)
  • DV Challenges — What challenges did you face as a DV engineer?
  • Coursework — Parallel comp arch course vs advanced micro-architecture course discussion
  • Cache Coherence — Project overview on cache coherence
  • MSI vs MESI — Differences between the protocols
  • MSI Walk-through — Example with reads and writes to a cache line
  • LRU Implementation — Explain LRU with example
  • Course Project — Deep discussion on a specific course project
  • Async Flip-Flop — Write an asynchronous flip-flop in Verilog
  • Count Ones — Count the number of 1s in binary format of a number
🍎 Apple — Pixel SoC DV

Apple Pixel SoC DV — Interview Questions

Mix of UVM, SV coding, constraints, LeetCode, and OOP

📞 Apple Pixel SoC DV — All Questions

Apple
  • Virtual Functions — Behavior in extended classes
  • Latency Calculation — Given 2 arrays of sent & received message timestamps: calculate latency of each, max latency, and pending messages
  • Factory Override — Describe a case where UVM factory override won't work
  • Test Plan — Write a test plan for single-port R/W memory with clock, reset, data, wr_en, rd_en, addr
  • UVM Monitor + Scoreboard — Write code that handles multiple outstanding out-of-order transactions
  • Concurrent Transactions — Write code to send & receive txns simultaneously (fork-join)
  • Constraints — Allocate non-overlapping address regions
  • LeetCode — Valid palindrome
  • Bug Discussion — Describe a bug you have faced
  • SV Typedef + Constraints — Model colors with typedef, constrain so last 3 don't repeat
  • Casting — Downcasting/upcasting behavior
  • LeetCode — Reverse digits of a number
  • 2D Canvas — Allocate rectangular regions randomly such that all pixels are covered
  • Debug Code — Find error in SV code that forks non- vs automatic tasks
  • Debug Code — Find error in SV code with non-blocking thread issues
  • Constraints — Constrain upper and lower nibbles of bytes
  • MUX Design — Enhance a mux design (use ternary to handle X's)
  • UVM Basics — What is the entry point of running a test?
  • Puzzle — Coin weighing problem
🍎 Apple — DV Panel Interview (Detailed)

Apple DV — 6-Round Panel Interview

Full experience with constraints, C++, MESI, UVM, and Verilog synthesis questions

📞 Screening — Singleton, UVM, Pipeline, MUX

Screening
  • Singleton Class — Implement singleton class in SV
  • UVM Objections — If you don't raise any objection, what happens to simulation?
  • Pipelining — Couple of pipeline questions
  • MUX Logic — Implement XOR using MUX. Implement NOT using MUX.
  • Coding — Write code for Fibonacci series

🔴 Round 1 — Constraints + C++ + Virtual Functions

Constraints
  • Constraints + Probability — Given bit t and int x, constrain x between ranges for t=0 and t=1. How does probability of x get affected? Use solve t before x
  • C++ Coding — Reverse bits of an integer
  • Virtual Functions — Explanation and usage in SystemVerilog
  • Python Challenge — Given a function returning float between 0-1, generate a random one-hot number

🔴 Round 2 — Memory + Bit Counting + DUT Verification

Coding
  • Memory Sweep — Generate address range and sweep length to cover full memory using a for loop
  • Count 1s — Find number of 1s in a bit pattern (n&(n-1) method, then recursive)
  • DUT Verification — Given a DUT, how to check if appropriate response is coming?

🔴 Round 3 — LeetCode + MESI + UVM Deep Dive

Arch + UVM
  • LeetCode — Simple version of 3Sum
  • MESI Protocol — 2 processors accessing a cache line. Given MESI state transitions, determine the read/write order
  • UVM Deep — Deep dive into UVM specifics
  • Synthesis Questions:
    always@(posedge clk) b<=a; c<=b; d<=c; → 3 FFs
    always@(posedge clk) b=a; c=b; d=c; → 1 FF
    always@(*) b=a; c=b; d=c; → Wire

🔴 Round 4 — Edge Detector + Constraints

RTL + SV
  • Waveform → Code — Write Verilog for an edge detector from a waveform
  • Constraints — Generate word-aligned, non-overlapping addresses
  • OOP — Base class assigned to derived and vice versa. Which is legal? How to force with $cast?

🔴 Round 5 — LeetCode + Constraints + Architecture

Mixed
  • LeetCode Two Sum — Handle duplicates edge case
  • Constraint — Only 2 bits set in a 6-bit number without $countones. Make generic for n bits.
  • Matrix Constraint — Column i and row i together have unique elements in NxN matrix
  • Hazards — Types of hazards, resolution, pros/cons of OoO execution
  • Race Condition — Two always blocks with cnt=50 and cnt=cnt-1. Value of cnt? Blocking vs non-blocking?

🔴 Round 6 — UVM Driver + Scoreboard

UVM
  • Memory Addressing — Generate non-overlapping addresses for read/write
  • UVM Driver — Write driver code for memory transaction with wr_rd, wr_data, addr, acknowledgement
  • UVM Scoreboard — Handle out-of-order reads and writes with separate queues
🍎 Apple — DV (3 YOE)

Apple DV — 3 Years Experience — 5-Round Panel

Serializer/deserializer IP, GLS, power aware sims, assertions, RTL design

📞 Screening — RAL, Constraints, Clock Glitch

Screening
  • Cache Line Select — In a single line of code, select a 32b word from a 512b cache line
  • RAL Polling — Loop polling a register with RAL get() but never getting the value. What's the reason?
  • Constraints — If x=1, y is in one range with distribution; if x=0, different range. Implication operator from solver's perspective
  • RAL Benefits — What is RAL? Benefits?
  • Clock Glitch Detection — Check for glitches on a clock within a tolerance range. Code it.
  • Bug Story — Describe a good bug you found recently

🔴 Round 1 — SerDes TB Design + GLS

UVM TB
  • TB Design — Design UVM testbench for serializer/deserializer IP. Code driver and interface. Interviewer kept modifying spec.
  • GLS Adaptation — Given setup/hold time requirements for GLS, how to modify TB?
  • IP → SoC — Handing off IP-level verification to SoC-level — what considerations?

🔴 Round 2 — Hiring Manager (Coverage + Power)

Discussion
  • Project Discussion — Most recent project deep dive
  • Coverage — Types implemented, benefits/pitfalls, specific examples
  • Power Aware Sims — UPF, isolation cells, level shifters, retention cells, power domains
  • OOO Scoreboard — Scoreboard for logic with OOO input/output. Multiple writes to same address before read?
  • Constraint — Protocol with address, payload (32-bit packets, 32-1024 packets), even parity bit

🔴 Round 3 — OOP + Assertions + Ring Buffer

SV/SVA
  • OOP Deep Dive — Inheritance, polymorphism, static/dynamic casting, cross-class object access (many scenarios)
  • Assertions — Write ALL assertions for a 4-way req/ack handshake. All assertion methods.
  • Assertion Timing — At what time is assertion sampled/evaluated? Drew waveforms.
  • Ring Buffer — How to verify empty/full scenarios?

🔴 Round 4 — RTL Design (Hardest Round)

RTL Heavy
  • Blocking/Non-blocking — Two always blocks with y1=y2 and y2=y1. Multiple variations.
  • Clock Gating — Code a glitch-free enable signal to gate a clock. Guarantee no metastability.
  • Clock MUX — Code a glitch-free clock switching mux (very difficult — interviewer admitted it)
  • Constraints — Non-overlapping memory regions in 1KB memory
  • Timeout — Call a process but only wait 30 clock cycles. How? (fork/join_any + disable fork)
  • disable fork — Concerns about using and not using disable fork
  • Fork Loop — For loop with fork/join, variable assignment. What's the issue? (kept modifying)

🔴 Round 5 — Easiest Round (Fundamentals)

Quick Hits
  • AND from MUX — Implement AND gate from 2:1 MUX
  • Time Precision — TB precision 1.0ps, always block loops every #1.0fs. What happens?
  • Static Counter — Track how many times a class is created (static variable)
  • Nyquist — 4KHz signal, minimum sampling frequency?
  • Coding — Track current max value from continuous voltage stream
  • Coding — Track moving average from continuous voltage stream
  • UVM Driver — Driver that sends packets immediately from sequencer (try_next_item), simultaneously checks DUT responses, matches to driven packets, sends response back
💙 Intel — DV Interview

Intel DV — Interview Questions

UVM testbench design, TLM, scoreboard, Python linked list, SV coding

🔵 Intel DV — All Questions

Intel
  • UVM TB Design — Draw UVM component TB for a 1-input, 2-output DUT
  • UVM Component vs Object — Differences?
  • TLM Connection — How to connect monitor to scoreboard? Explain TLM and write function
  • Full Scoreboard — Write complete scoreboard with uvm_analysis_imp_decl and uvm_tlm_analysis_fifo. Can you use golden reference model in write() method itself?
  • Reset Types — Sync vs async reset, unique case, casez
  • SV Checker — Write a SystemVerilog checker
  • Verification Plan — Write a verification plan for two FIFO queues
  • Python Linked List — Given a LinkedList class, determine what functions A-E do (add head, remove tail, remove head, add tail, change value at index, insert at index)
  • Linked List Size — Write function to return size of linked list
  • Soft Constraints — Explain. Difference between := and :/ operators
  • Bit Reversal — Function to return reversed bit pattern: return {<<{arr}};
  • Fibonacci — Write function returning greatest Fibonacci number smaller than input N
  • Edge Detector — Write positive edge detector for a signal in Verilog
💚 NVIDIA-Style — GPU DV Comprehensive

GPU DV — Comprehensive Question Bank

Architecture, CDC, Verilog/SV, UVM, Constraints, Test Planning — from multiple rounds

🏗️ Computer Architecture & CDC

Arch
  • Virtual Memory, TLB, Page Table Walk Through
  • Page Fault Exceptions
  • Out-of-Order Processor with Branch Prediction & interrupt/fault recovery
  • 5-stage pipeline processor control unit
  • Memory Coherence Protocols (MSI, MESI, MOESI)
  • CDC: Recirculating Mux, FIFO, Handshaking mechanism design
  • CMOS capacitance, delays, power dissipation
  • UPF Retention registers
  • Identify setup/hold violations in a circuit and redesign to fix
  • Design a digital block to remove data glitches

💎 Verilog / RTL Coding

Verilog
  • Edge detector — synthesizable code without posedge construct
  • Edge detector FSM (Moore & Mealy)
  • Signal high for exactly one clock period on input rising edge
  • Synchronous multiplier (32-bit, result within 1000 clocks)
  • Waveform → synthesizable Verilog (AMBA APB Slave style)
  • Given Verilog code → count flops and latches after synthesis
  • == vs === operators
  • Multi-driver code → redesign to eliminate X
  • Identify coding issues (missing else → latch, syntax errors)
  • Fork-join with for loops inside fork-join_none
  • Blocking vs NBA waveform questions (transport vs inertial delay)

🔧 SystemVerilog & UVM

SV + UVM
  • Watchdog timer — if signal not high within 100 sec, alert and reset system
  • Polymorphism — ~14 questions on different configurations!
  • Constraints — soft keyword, conflicts, enable/disable, power-of-2 address, address+offset inside memory range
  • Generate unique random address across different class handles
  • Semaphores, Mailboxes
  • Monitor and Scoreboard from waveform + blackbox
  • Debug SV code — find compile and runtime errors
  • Coverage — Subscriber class
  • UVM: config_db vs resource_db, TLM (get/put/blocking/non-blocking/fifo)
  • Two analysis_imp ports in one class — how to resolve two write() functions?
  • Virtual sequence/sequencer, lock/unlock/grab/ungrab
  • UVM phases execution order
  • Sequence priority settings, verbosity control

📋 Test Planning & Methodology

Planning
  • Develop test plan for a black box
  • Verification strategy — prioritizing tasks
  • Management scenarios — designer on leave, unclear clock frequency
  • Debug approaches
🎓 NCG Screening — Common Questions

New College Grad — Screening Round Questions

Commonly asked in phone screens and initial coding rounds

📞 NCG Screening Questions

Screening
  • Constraints — Generate even and odd numbers. Add 70/30 distribution.
  • Checker Function — Find if an even number was generated by DUT in past 10 outputs
  • Fork/Join — Difference between fork-join, join_none, join_any
  • Fork Puzzle — fork begin for(i=0;i<3;i++) print(i); join_none vs for loop with fork/join_none inside. What prints?
  • Events/Semaphores — Applications in fork-join_none
  • Array Constraint — Array of size N, random numbers A and B are repeated A and B times
📚 Frequently Asked — All Companies

Most Commonly Asked DV Interview Questions

These questions appear across multiple companies — the must-know list

🏗️ Architecture & Digital Logic

High Freq
  • Virtual memory, TLB, page table walk
  • Cache design, indexing, VIPT cache
  • Pipeline hazards (RAW/WAW/WAR) and solutions
  • Out-of-order execution, register renaming, ROB
  • Memory coherence (MSI, MESI, MOESI)
  • CDC — synchronizer design, async FIFO
  • Setup/hold time, violations, fixes
  • Flip-flop vs latch
  • FIFO depth calculation (given read/write frequencies)
  • Find SA0/SA1 among 128 wires in minimal steps

💎 SystemVerilog & UVM

High Freq
  • Blocking vs non-blocking assignments
  • Fork-join / join_any / join_none
  • Task vs function
  • Packed vs unpacked arrays, associative arrays
  • Polymorphism, virtual functions, upcasting/downcasting
  • Static vs automatic variables
  • Deep copy vs shallow copy
  • uvm_object vs uvm_component
  • Concurrent vs immediate assertions
  • Coverage: code vs functional, covergroups, cross coverage
  • Scoreboard structure and implementation
  • Sequencer structure, `uvm_do macro
  • RAL model — adapter and predictor
  • UVM phases, objections, config_db
  • Write SV assertion for req/ack protocol
  • Verification plan for any given design

🔄 RTL / FSM / Verify

High Freq
  • FSM: divisible by 5, sequence detector (101, 1011)
  • Logic gates using MUX and NAND
  • Full adder circuit + count 1s in 7-bit array using full adders
  • 3-bit shift register in Verilog
  • FIFO test plan and assertions
  • How to verify L3 cache + main memory model
  • Priority encoder in Verilog
  • XOR gate from MUX
  • Verify packet processing DUT with priority
  • Cache design: 32KB, 40-bit address, 64B line, 4-way — bits for true LRU?
  • Simplify circuit (adders + MUX → adder with input MUXes)
  • UVC mimicking memory, reactive sequence in UVM

💻 Coding / LeetCode

High Freq
  • Reverse a linked list
  • Count 1s in a 32-bit number
  • Reverse all bits of a 32-bit number
  • Fibonacci series (recursive & optimized)
  • Merge sort
  • 2D matrix 90° rotation in-place
  • Find repeating element in array (Floyd's algorithm)
  • Second largest number in array
  • Odds left, evens right — in O(n)
  • LIFO using queues only
  • Common elements between arrays — optimize complexity
  • Random number generator in C++ — reduce complexity
  • Generate unique random array of size 1000 (without unique keyword)
  • Generate number with exactly x bits set
  • Implement distribution using only $urandom
  • Throughput comparison: 1 unit (9ns) vs 3 pipelined units (2ns+4ns+3ns)

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